Generally, in a volatile semiconductor memory device such as a DRAM, a refresh operation is required to prevent data loss.
This is because a cell capacitor to form a unit cell of a data storage does not have an ideal data storage feature, that is, because stored charges in the capacitor disappear with a leakage current shortly after a write operation.
Accordingly, before the stored data are fully extinguished, a refresh operation which verifies and restores the data has to be carried out.
FIG. 1 is a timing chart illustrating a refresh operation in a conventional memory device. Referring to FIG. 1, when an all-bank refresh mode to simultaneously refresh all banks is carried out, an enable timing of each bank is differently taken in order to reduce a peak current.
That is, the conventional refresh method reduces the peak current by sequentially delaying the enable timing of each bank in the all-bank refresh mode.
FIG. 2 is a graph illustrating a peak current characteristic in the conventional refresh of FIG. 1. Referring to FIG. 2, the peak current of the refresh can be dispersed by making bank enable timings different from each other.
However, in this refresh operation, the data refresh section is relatively short in the rest of the banks except for a first enabled bank so that they are different from each other in the refresh features according to the shortness of the refresh section. This phenomenon increases an auto refresh time and there is a possibility that the refresh deteriorates according to the characteristic difference between the banks in case of a normal refresh mode.